The present invention relates generally to the field of radio frequency identification (RFID) devices or tags and specifically to RFID devices which include one or more persistent nodes.
RFID transponders (commonly referred to herein as “tags”) in the form of labels, inlays, straps or other forms are widely used to associate an object with an identification code. Tags generally include one or more antennas with analog and/or digital electronic circuits that include communications electronics (such as an RF transceiver), data memory (for storing one or more identification codes), processing logic (such as a microcontroller) and one or more state storage devices. Examples of applications that can use RFID tags include luggage tracking, inventory control or tracking (such as in a warehouse), parcel tracking, access control to buildings or vehicles, etc.
There are three basic types of RFID tags. A passive tag is a beam powered device which rectifies energy required for operation from radio waves generated by a reader. For communication, the passive tag creates a change in reflectivity of the field which is reflected to and read by the reader. This is commonly referred to as continuous wave backscattering. A battery-powered semi-passive tag also receives and reflects radio waves from the reader; however a battery powers the tag independent of receiving power from the reader. An active tag, having an independent power supply, includes its own radio frequency source for transmission.
The reader, sometimes referred to as an interrogator, includes a transmitter to transmit RF signals to the tag and a receiver to receive tag modulated information. The transmitter and receiver can be combined as a transceiver which can use one or more antennas. Communications between a reader and tag is defined by an air interface protocol, such as (without limitation):
(i) EPCglobal's EPC Radio-Frequency Identity Protocols Class-1 Generation-2 UHF RFID Protocol for Communications at 860 MHz-960 MHz, version 1.2.0 (http://www.epcglobalinc.org/) (hereinafter referred to as the “UHF Gen2 standard”);
(ii) adaptations of the UHF Gen2 standard for operation at high frequency (“HF”), for example at 13.56 MHz; and
(iii) ISO/IEC 18000-6 Information technology—Radio frequency identification for item management—Part 6: Parameters for air interface communications at 860 MHz to 960 MHz, Amendment 1: Extension with Type C and update of Types A and B. Each of the above protocols is incorporated herein by reference for all purposes.
Communication protocols, such as these, may require that a passive tag operate a timing circuit or maintain a flag value during a brief lapse of received power which can occur when a reader hops between transmission frequencies. For example, the UHF Gen2 standard requires persistence for flags SL, S1, S2, and S3, but not S0. U.S. Pat. No. 6,942,155 and pending U.S. application Ser. No. 12/420,009, filed Apr. 7, 2009, both assigned to Alien Technology Corporation (“Alien,” also the assignee to this invention) and incorporated by reference herein for all purposes, provide various teachings on persistent flags and nodes. Other or related techniques have been suggested by the following patents (each of which is incorporated by reference herein for all purposes): U.S. Pat. No. 7,259,654; U.S. Pat. No. 7,710,798; and U.S. Pat. No. 7,215,251.
It should be clear from the teachings herein that a persistent flag is a bit, character(s), or other indicator that signals the occurrence of some condition. The persistent flag can be stored in a persistent node that provides a state storage device. The persistent node is a circuit which is initialized to a value, and the value read from the persistent node can change at some later time. Persistent flags can be implemented using persistent nodes as described in one or more of the incorporated references. As an example, persistent flags can be implemented essentially as a timer using persistent nodes. For example in the ISO/IEC 18000-6c specification, each flag has one of two values. “A” or “B” for the S1, S2 or S3 flags, and “asserted” or “deasserted” for the SL flag.
Passive RFID tags can lose power whenever a reader is turned off for a period of time that is longer than the tag can support supplying current from its power capacitor(s). Currently known methods of implementing a state storage bit or flag in a state storage device include the use of an FET (Field Effect Transistor) to charge/discharge a capacitor so that the leakage through the FET in the off state determines the discharge time for the state storage bit. Since the high impedance of the FET (in the off state) depends on parasitics, when the power supply is off (e.g., the reader stops transmitting), the state storage device dissipates its charge by means of an unknown and widely varying leakage current. As a result, these implementations can cause the capacitor to drain current too quickly or allow the capacitor to retain a charge for too long. Hence, in these implementations, the state storage time can vary with ambient temperature (e.g. tags in a cold warehouse vs. tags in a hot warehouse will have different state storage times) and can vary due to processing variations (from variations in processing operations in the semiconductor wafer and IC fabrication process), and this variation can be from a few seconds to a few hours. A known method of reducing the variation of the current discharging device is the use of a calibration method to keep a FET transistor gate bias blocking the discharge of the capacitor at a voltage which gives a substantially constant current; another known method to reduce this variation is to trim the devices to minimize process variations. These known methods either result in significant variation in the timing of the circuit or substantial additional cost due to additional semiconductor IC fabrication processing or additional circuit area to provide calibration circuits.
FIG. 1 shows an example in the prior art which uses a thin oxide capacitor as a state storage device for an RFID tag. The state storage device 11 in FIG. 1 includes an n-channel FET 12 having its drain coupled to a supply voltage Vdd (or to another charging or discharging node which supplies a voltage derived from a voltage source) and its gate 14 coupled to processing logic (not shown) to either charge or not charge the capacitors 15 and 16 which are coupled, at node 19, to the source of FET 12. The capacitors 15 and 16 are also coupled to Vss (which can be ground). The FET 12 acts as a switch, which is controlled by the signal applied to gate 14, to either charge or not charge the capacitors 15 and 16. Capacitor 16 is a thin gate oxide capacitor which supplies the majority of the capacitance due to its thin dielectric, and also allows current through the dielectric due to tunneling; the capacitor 16 is disposed in the substrate of a semiconductor IC (integrated circuit) that includes the state storage device 11. Capacitor 15 is a capacitor fabricated in the metal and insulator layers above the substrate and hence capacitor 15 is referred to as a metal-insulator-metal (MIM) capacitor. The capacitance of capacitor 16 exceeds the capacitance of capacitor 15. Node 19 can be considered the output of the state of the state storage device 11, and this output is coupled to one input of a balanced sense amp 18 that also receives an input from a set of capacitors 15A and 16A that are fabricated to match identically capacitors 15 and 16. Capacitors 15A and 16A remain at a fully discharged state, and the balanced sense amp 18 determines whether the output at node 19 exceeds the fully discharged state of capacitors 15A and 16A. The balanced sense amp 18 is implemented as a current mirroring circuit that flips an output one way or the other way depending upon whether the node 19 exceeds the fully discharged state of capacitors 15A and 16A. The balanced sense amp allows discharge to a very low level, and the time to discharge of the node depends on the total capacitance of capacitors −15 and 16, the semiconductor leakage through the FET 12 at high temperatures, and the leakage through the oxide of cap 16 at low temperatures. The time to discharge varies from below 1 second at high temperatures, limited by leakage through FET 12, and over 120 seconds at low temperatures, limited by the leakage of cap 16. The process variation is also approximately a factor of 5, due to the discharge to very low level, maintaining an adequate persistent node duration.